The Jha lab focuses on Artificial Intelligence and Emerging Computer Architectures
Our research is being supported by a number of sponsors:
- National Science Foundation Computing and Communications Foundations — Scalable Parallelism in the Extreme (SPX)
- Florida Cybersecurity Center Collaborative Seed Award
- US Air Force Research Laboratory
- Oak Ridge National Laboratory
- Royal Bank of Canada
- UCF Predictive Analytics Innovation Fellowship
- Air Force Office of Scientific Research Young Investigator Award
- National Science Foundation Computing and Communications Foundations — Exploiting Parallelism & Scalability
- National Science Foundation Computing and Communications Foundations — Software & Hardware Foundations
NSF award for our research into emerging architectures
The transistor density of integrated circuits has been doubling approximately every two years for about four decades. This exponential rise in the computational power of the integrated circuit has driven the information technology revolution that has transformed every aspect of our society - from personal entertainment devices to high-assurance intelligent cyber-physical systems. However, the growth in transistor density is now slowing down, and new technological breakthroughs are urgently needed to sustain the ongoing information technology revolution.
Our ongoing research creates a new memristor-based nano-computing architecture that circumvents the fabrication density problems associated with traditional transistor-based integrated circuits. We investigate the fundamental principles of memristor-based nano-computing and designs efficient memristor-based nano-crossbar circuits that can execute elementary bit-vector mathematical and logical computations. We are pursuing a transformative agenda for extreme-scale computing that involves two design principles: (1) the use of memristors as distributed asynchronous digital switches and continuous-valued non-volatile nano-stores of input data and intermediate results, and (2) the use of sneak-paths in nano-crossbars as fundamental computational primitives that pool together results of intermediate computations from distributed memristor nano-stores.
The memristor-based nano-computing architecture will enable the execution of legacy programs on low-energy ultra-dense memristive nano-crossbar circuits and will facilitate the design of domain-specific parallel execution engines that combine storage and computation on the same chip - thereby nullifying the traditional barrier between the memory and the microprocessor.